1. Technical Field
The present invention relates to a method of producing a semiconductor device, and more particularly to a structure and a production method for an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor comprising a pillar-shaped semiconductor layer having a sidewall serving as a channel region, and a gate electrode formed to surround the channel region.
2. Background Art
With a view to achieving higher integration and higher performance of a semiconductor device, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see Patent Document 1: JP 2-188966A). In the SGT, a source, a gate and a drain are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
FIG. 22(a) shows a top plan view of a CMOS inverter configured using the SGT disclosed in the Patent Document 1, and FIG. 22(b) is a sectional view taken along the cutting-plane line A-A′ in the top plan view of FIG. 22(a).
Referring to FIGS. 22(a) and 22(b), an N-well 302 and a P-well 303 are formed in an upper region of a Si substrate 301. A pillar-shaped silicon layer 305 forming a PMOS (PMOS-forming pillar-shaped silicon layer 305) and a pillar-shaped silicon layer 306 forming an NMOS (NMOS-forming pillar-shaped silicon layer 306) are formed on a surface of the Si substrate, specifically on respective ones of the N-well region and the P-well region, and a gate 308 is formed to surround the pillar-shaped silicon layers. Then, each of a P+ drain diffusion layer 310 formed beneath the PMOS-forming pillar-shaped silicon layer, and a N+ drain diffusion layer 312 formed beneath the NMOS-forming pillar-shaped silicon layer, is connected to an output terminal Vout. A source diffusion layer 309 formed on a top of the PMOS-forming pillar-shaped silicon layer is connected to a power supply potential Vcc, and a source diffusion layer 311 formed on a top of the NMOS-forming pillar-shaped silicon layer is connected to a ground potential Vss. Further, the gate 308 common to the PMOS and the NMOS is connected to an input terminal Vin. In this manner, the CMOS inverter is formed.
As one example of an SGT production method, a process flow is disclosed in the following Non-Patent Document 1. FIG. 23 show a schematic process flow for forming a pillar-shaped silicon layer and a gate electrode in an SGT disclosed in the Non-Patent Document 1. The following description will be made about this process flow. As shown in FIG. 23(b), a silicon substrate 402 illustrated in FIG. 23(a) is etched to form a pillar-shaped silicon layer 403. Then, as shown in FIG. 23(c), a gate dielectric film 404 is formed. Then, as shown in FIG. 23(d), a gate conductive film 405 is formed. Then, as shown in FIG. 23(e), the gate conductive film 405, and a portion of the gate dielectric film 404 on a top of the pillar-shaped silicon layer, are polished by chemical mechanical polishing (CMP). Then, as shown in FIG. 23(f), the gate conductive film 405 is etched back in such a manner that the gate conductive film 405 surrounding the pillar-shaped silicon layer is fabricated to have a desired gate length. Then, as shown in FIG. 23(g), a resist 406 for a gate line pattern is formed by lithography. Then, as shown in FIG. 23(h), the gate conductive film 405 is etched to form a gate electrode and a gate line.    Patent Document 1: JP 2-188966A    Non-Patent Document 1: Ruigang Li, et al., “50 nm Vertical Surround Gate MOSFET with S-Factor of 75 mV/dec”, Device Research Conference, 2001, p. 63.
However, the SGT production method illustrated in FIG. 23 has the following problem. During dry etching for forming a gate electrode in the above process flow, an etching end-point has to be based on a designated etching time, because it is unable to employ an end-point detection process based on monitoring a change in plasma emission intensity. In this case, during the dry etching, a variation in etching rate of an etching apparatus in each lot or in each wafer has a direct impact on gate length to cause a significantly large variation in gate length. The larger variation in gate length undesirably leads to a larger variation in transistor characteristics.
Thus, in order to reduce a variation in SGT characteristics, it is essential to employ an end-point detection process capable of absorbing the variation in etching rate in each lot or in each wafer.
In view of the above circumstances, it is an object of the present invention to produce an SGT with a stable gate length, using an end-point detection process based on monitoring a plasma emission intensity during dry etching for setting a gate length.